Computer Organization

CSCE 2214

Class Description

Design and implementation of a standard Reduced Instruction Set (RISC) microprocessor and supporting memory hierarchy. Detailed analysis of instruction set encodings and efficient pipelined implementation of the instruction set including data and control hazards introduced by pipelining instruction execution. Introduction to Memory Hierarchy including technology issues for main memory, and cache organization. The Laboratory component allows students to apply classroom theory by designing and implementing a complete working pipelined CPU, and evaluating cache organizations through a simulator.

 

Textbook

  1. Computer Organization and Design, Fifth Edition. By David Patterson and John Hennessy. ISBN 0123744938